This invention relates to phase locked loop frequency synthesizers, and in particular to a phased locked loop frequency synthesizer that operates in offset mode in cooperation with a second phase locked loop to reduce the divide ratio of the phase locked loop.
The use of a phase locked loop (PLL) as a frequency synthesizer is well documented in the literature. Often it is desired to make the frequency synthesizer programmable for different frequencies that might, for example, correspond to different channels in a wireless receiver or wireless transmitter. One conventional implementation of a circuit for doing this is shown in FIG. 2A, and includes in the feedback loop a voltage controlled oscillator (VCO), a divider (divide-by-N circuit), a phase detector to compare the phase of the output of the divider to that of a reference oscillator, a charge pump, and a loop filter. In this way the output of the VCO is divided by an integer N before it is compared to the reference input by the phase comparator. In order for the loop to lock, both the reference input and the divided VCO output must be identical in both phase and frequency. To achieve this, the loop must maintain the output of the VCO at a frequency that is N times greater than that of the reference input.
It often is desired to make the divide ratio of the divider programmable by using a programmable divider that provides slightly different frequencies, e.g. frequency channels. A programmable divider is a relatively complicated circuit that has limited frequency capability. When implemented in CMOS, for example, the programmable divider includes many MOS transistors connected to relatively few nodes, resulting in a total capacitance per node that limits the frequency capability of the programmable divider.
Wireless local area networks (WLANs) that operate at high frequencies, e.g., in the 5 GHz band, are now being introduced. See, for example, the IEEE 802.11a and the European HIPERLAN I and II standards for WLANs in the 5 GHz band. There thus is a need for wireless receivers and transmitters that operate in the 5 GHz range. Such receivers and transmitters typically use a local oscillator. There thus is a need for a frequency synthesizer that operates in the 5 GHz range. A typical CMOS programmable divider operates up to a frequency lower than 5 GHz. The inventors have found, for example, that with a standard 1.8-volt CMOS process (Taiwan Semiconductor Manufacturing Co., Ltd.), a typical programmable divider operates to about 2 GHz.
One prior art technique for building a frequency synthesizer capable of generating a signal in the 5 GHz range using a 2 GHz capable programmable divider is to add a second divider acting as a prescaler, e.g., a divide by 4 prescaler between the voltage controlled oscillator and the programmable divider as shown in FIG. 2B. The programmable divider would then only need to operate at a range of 5/4 GHz, which is within its range, e.g., for a 1.8 volt CMOS process. The overall divide ratio of the loop is then 4N where N is the divide ratio of the programmable divider.
Having a large divide ratio, however, increases the overall phase noise. The contribution to the overall phase noise of the reference oscillator, for example, might be 4N times the phase noise of the reference oscillator. The phase detector and the charge pump also make a contribution to the noise. Thus the higher the divide ratio, the higher the overall phase noise.
Thus there is a desire to minimize the overall divide ratio of the PLL in a PLL frequency synthesizer, but still use a limited-frequency programmable divider.
There is a constraint in maintaining the channel set-size requirements that also limits the architecture. For example, suppose that the comparison frequency at the phase detector is in the 5 MHz range. Because of the divide-by-4 prescaler, minimum step size will be 5xc3x974=20 MHz, which may be too high for some applications. For example, a radio receiver or transmitter in the European UNI-3 band need have a step size of 5 MHz. This would require a comparison frequency at the phase detector of 5/4=1.25 MHz.
In a typical design, in order to avoid leakage from the reference source, a good rule of thumb is to use PLL with a loop bandwidth at most about {fraction (1/20)}th of the comparison frequency. The 5 MHz channel requirement with the prior-art architecture of FIG. 2B would then lead to a very low loop bandwidth, e.g., 1.25 Mhz/20=60 kHz. Such a low loop bandwidth is not desirable because, for example, the dynamic response of the loop may then be poor. Consider, for example, using the PLL and switching channels. Having a relatively low loop bandwidth restricts the switchover time from one channel to another. A high bandwidth further is desirable for shaping of the phase noise spectrum to obtain some desirable phase noise reduction.
Thus there is a need for a PLL frequency synthesizer architecture that meets the phase noise, channel step size, and channel switching time requirements for WLAN (and other) applications, particular for WLANs than meet one or more of the upcoming high frequency WLAN standards.
For more information on the IEEE 802.11 and IEEE 802.11 a standards, see: ANSI/IEEE Std 802.11, 1999 Edition (ISO/IEC 8802-11:1999) Local and metropolitan area networksxe2x80x94Specific Requirementsxe2x80x94Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, and IEEE Std 802.11a-1999 [ISO/IEC 8802-11: 1999/Amd 1:2000(E)] (Supplement to IEEE Std 802.11, 1999 Edition) Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHz Band. The standards are available on the Internet at several locations, including from the IEEE (www.IEEE.org) and in particular at http://grouper.ieee.org/groups/802/11/index.html.
Described herein is a phase locked loop (PLL) frequency synthesizer that includes a voltage controlled oscillator (VCO) to provide a VCO frequency signal, a frequency offset circuit including a mixer accepting the VCO frequency signal and a signal from a second oscillator to produce a shifted-frequency signal having a frequency significantly lower than the VCO output frequency, a programmable divider accepting the shifted-frequency signal and dividing the frequency of the shifted-frequency signal by a settable amount, a phase detector to compare the phase of the output of the programmable divider to that of a reference oscillator and produce a phase difference signal; and a loop filter to filter a function of the phase difference to produce a control input to the VCO. The offset circuit shifts down the frequency without increasing the divide ratio of the loop as would a prescaler achieving the same frequency conversion as the frequency offset circuit.